1. Technical Field
The present invention relates in general to the field of static random access memory (SRAM) and in particular to SRAM decoders with write assist.
2. Description of the Related Art
As memory devices such as SRAM achieve increasingly smaller line sizes, normal variations in the devices introduced by the production processes become increasingly significant. Production variations may narrow the effective voltage range of a memory device's centering window, reducing the difference between the voltage required to retain stable data within a memory cell and the voltage required to update the memory cell. The reliability of the memory device can therefore be diminished.
A variety of techniques have been adopted in SRAM design to increase memory stability in the presence of narrowed write window. One technique that has been effective is to apply a lower cell supply voltage during a WRITE operation and a higher cell supply voltage during a READ operation. In order to provide more than one cell supply voltage, an additional power supply circuit may be implemented in the SRAM or a chip reference voltage regulator may be used to generate a lower cell supply voltage for use during WRITE operations. However, adding one or more additional voltage supplies to the SRAM can be cost prohibitive in at least some applications, and use of an on-chip reference voltage regulator is generally not power efficient.